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[Other resource] ref-ddr-sdram-vhdl

Description: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Platform: | Size: 1031656 | Author: 包盛花 | Hits:

[Other resource] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776642 | Author: 张涛 | Hits:

[Other] ref-ddr-sdram-vhdl

Description: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Platform: | Size: 437055 | Author: kevin | Hits:

[Other resource] very-good-ok-ref-ddr-sdram-verilog

Description: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Platform: | Size: 895594 | Author: 姚明 | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
Platform: | Size: 131072 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl

Description: 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
Platform: | Size: 1031168 | Author: wfs | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA-DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
Platform: | Size: 676864 | Author: 黄达 | Hits:

[VHDL-FPGA-Verilog] 512Mb_ddr_Modules

Description: DDR and DDR DIMM Controller
Platform: | Size: 23552 | Author: starplus | Hits:

[VHDL-FPGA-Verilog] DDRctroll

Description: ddr 的fpga 控制器的实现 仿真正确-ddr controller fpga to achieve the correct simulation
Platform: | Size: 3970048 | Author: gongranli | Hits:

[VHDL-FPGA-Verilog] tips_vhdl

Description: 包含图像采集、i2c设计及混合语言仿真、DDR控制器以及一些小程序，供学习使用-Includes image acquisition, i2c design and mixed-language simulation, DDR controller, and a number of small programs for learning to use
Platform: | Size: 7177216 | Author: 陈少华 | Hits:

[SCM] DDRcontrol

Description: DDR控制器的设计参考，包含有中文说明文档-DDR controller design for reference, including documentation in Chinese
Platform: | Size: 475136 | Author: 林果 | Hits:

[source in ebook] xapp702

Description: 用Virtex4系列FPGA实现DDR控制器的技术介绍-With Virtex4 series FPGA to achieve DDR Controller Technology
Platform: | Size: 216064 | Author: 林果 | Hits:

[VHDL-FPGA-Verilog] ddr2_controller

Description: DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
Platform: | Size: 52224 | Author: yanxp | Hits:

[Embeded Linux] DS-0050_OXE800SE_datasheet

Description: SATA NAS SOC，200MHz ARM926EJS核 SATA接口的NAS用处理器，集成USB2.0 HOST接口，Ethernet控制器，DDR SDRAM控制器，PCI HOST接口，可以扩展PCI外设。-SATA NAS SOC，NAS COntroller with 200MHz ARM926EJS core, intergated SATA controller，USB2.0 HOST controller，Ethernet MAC controller，DDR SDRAM controller，PCI HOST。-The OXE800SE is a highly integrated, powerful network attached storage controller for bridging between Ethernet and SATA hard disks.
Platform: | Size: 317440 | Author: lzch | Hits:

[VHDL-FPGA-Verilog] DDR_prj

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA。-DDR controller VHDL source code. FPGA implementation using DDR interface controller for Altera' s FPGA.
Platform: | Size: 4781056 | Author: zhanghe | Hits:

[VHDL-FPGA-Verilog] sdram_controller_latest.tar

Description: sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.
Platform: | Size: 30720 | Author: Andrei | Hits:

[VHDL-FPGA-Verilog] ddr

Description: DDR SDRAM 控制器 VHDL代码，可支持32bits数据总线-VHDL code for DDR SDRAM controller, supporting 32bits data bus
Platform: | Size: 9216 | Author: chen | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM_controller

Description: ddr sdram控制器，lattice器件的参考设计，比较详细-ddr sdram controller, lattice components of the reference design, very detailed
Platform: | Size: 693248 | Author: | Hits:

[VHDL-FPGA-Verilog] ddr

Description: 基于FPGA的ddr控制器的设计与实现，verilog，ISE-FPGA-based controller design and implementation of ddr, verilog, ISE
Platform: | Size: 179200 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] 400-Mbs-DDR-Controller

Description: 这个应用描述了怎样在Xilinx环境下，通过MIG实现DDR控制器-Synthesizable 400 Mbs DDR SDRAM Controller
Platform: | Size: 290816 | Author: 吴言 | Hits:
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